? semiconductor components industries, llc, 2001 june, 2001 rev. 1 1 publication order number: mc74act564/d mc74act564 octal d-type flip-flop with 3-state outputs1 the mc74act564 is a highspeed, low power octal flipflop with a buffered common clock (cp) and a buffered common output enable (oe ). the information presented to the d inputs is stored in the flipflops on the lowtohigh clock (cp) transition. the mc74act564 device is functionally indentical to the mc74act574, but with inverted outputs. ? inputs and outputs on the opposite sides of the package allowing easy interface with microprocessors ? useful as input or output port for microprocessor ? functionally indentical to the mc74act574 but with inverted outputs ? 3state outputs for busoriented applications ? outputs source/sink 24 ma ? ttl compatible inputs marking diagrams tssop20 dt suffix case 948e 20 1 so20 dw suffix case 751d 1 20 act 564 alyw act564 awlyyww pdip20 n suffix case 738 1 2 0 mc74act564 awlyyww 20 1 20 1 20 1 http://onsemi.com device package shipping ordering information mc74act564dt tssop20 75 units/rail mc74act564dtr2 tssop20 2500 tape & reel mc74act564n pdip20 18 units/rail mc74act564dw soic20 38 units/rail mc74act564dwr2 soic20 1000 tape & reel a = assembly location l, wl = wafer lot y, yy = year w, ww = work week
mc74act564 http://onsemi.com 2 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 cp oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd figure 1. pinout: 20lead packages conductors (top view) pin assignment pin d 0 d 7 function data inputs cp clock pulse input oe 3state output enable input o 0 o 7 3state outputs figure 2. logic symbol o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 cp oe figure 3. logic diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 cd q o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 oe cp cd q cd q cd q cd q cd q cd q cd q please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. function table inputs internal outputs f nction oe cp d q o function h h l nc z hold h hh nc z hold h lh z load h hl z load l lh h data available l hl l data available l hl nc nc no change in data l h h nc nc no change in data h = high voltage level l = low voltage level x = immaterial z = high impedance = lowtohigh transition nc = no change
mc74act564 http://onsemi.com 3 functional description the mc74act564 consists of eight edgetriggered flipflops with individual dtype inputs and 3state complementary outputs. the buffered clock and buffered output enable are common to all flipflops. the eight flipflops will store the state of their individual d inputs that meet the setup and hold times requirements on the lowtohigh clock (cp) transition. with the output enable (oe ) low, the contents of the eight flipflops are available at the outputs. when oe is high, the outputs go to the high impedance state. operation of the oe input does not affect the state of the flipflops. maximum ratings (note 1) symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 2) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% 35% ul94vo (0.125 in) v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latchup latchup performance above v cc and below gnd at 85 c (note 6) 100 ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. 2. i o absolute maximum rating must be observed. 3. tested to eia/jesd22a114a. 4. tested to eia/jesd22a115a. 5. tested to jesd22c101a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc dc input voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types 40 25 +85 c t r , t f input rise and fall time (note 8) v cc = 4.5 v 0 10 10 ns/v t r , t f in ut rise and fall time (note 8) v cc = 4 . 5 v v cc = 5.5 v 0 0 10 8.0 10 8.0 ns/v t j junction temperature (pdip) 140 c i oh output current high 24 ma i ol output current low 24 ma 7. unused inputs may not be left open. all inputs must be tied to a high voltage level or low logic voltage level. 8. v in from 0.8 v to 2.0 v; refer to individual data sheets for devices that differ from the typical input rise and fall times.
mc74act564 http://onsemi.com 4 dc characteristics t a = +25 c t a = 40 c to +85 c symbol parameter v cc (v) typ guaranteed limits unit conditions v ih minimum high level i nput voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 v v v out = 0.1 v or v cc 0.1 v v il maximum low level input voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 v v v out = 0.1 v or v cc 0.1 v v oh minimum high level output voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 v v i out = 50 m a 4.5 5.5 3.86 4.86 3.76 4.76 v v *v in = v il or v ih 24 ma i oh 24 ma v ol maximum low level output voltage 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 v v i out = 50 m a 4.5 5.5 0.36 0.36 0.44 0.44 v v *v in = v il or v ih 24 ma i ol 24 ma i in maximum input leakage current 5.5 0.1 1.0 m a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc 2.1 v i oz maximum 3state current 5.5 0.5 5.0 m a v i (oe) = v il , v ih v i = v cc , gnd v o = v cc , gnd i old i ohd 2minimum dynamic output current 5.5 5.5 75 75 ma ma v old = 1.65 v max v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time. ac characteristics t r = t f = 3.0 ns (for figures and waveforms, see figures 4, 5, and 6.) t a = +25 c c l 50 pf t a = 40 c to +85 c symbol parameter v cc * (v) c l = 50 pf to +85 c c l = 50 pf unit min typ max min max f max maximum clock frequency 5.0 85 75 mhz t plh propagation delay cp to q n 5.0 2.0 10.5 1.5 11.5 ns t phl propagation delay cp to q n 5.0 1.5 9.5 1.5 10.5 ns t pzh output enable time 5.0 1.5 9.0 1.5 9.5 ns t pzl output enable time 5.0 1.5 8.5 1.0 9.5 ns t phz output disable time 5.0 1.5 10.5 1.5 11.5 ns t plz output disable time 5.0 1.5 8.0 1.0 8.5 ns *voltage range 5.0 v is 5.0 v 0.5 v
mc74act564 http://onsemi.com 5 ac operating requirements t a = +25 c t a = 40 c to +85 c s y mbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit symbol parameter v cc (v) typ guaranteed minimum unit t s setup time, high or low d n to c p 5.0 2.5 3.0 ns t h hold time, high or low d n to c p 5.0 1.0 1.0 ns t w c p pulse width high or low 5.0 3.0 3.5 ns *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50 pf v cc = 5.0 v switching waveforms figure 4. c p q t r t f 3.0 v gnd 50% 50% t plh t phl 50% data c p 3.0 v figure 5. valid gnd *includes all probe and jig capacitance c l * 50 scope test point device under test output figure 6. t w 1/f max v cc gnd t su t h 50% figure 7. test circuit 450 50% oe c p 3.0 v 3.0 v gnd t s t h 50% input
mc74act564 http://onsemi.com 6 package dimensions n suffix plastic dip package case 73803 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc dw suffix plastic soic package case 751d04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mc74act564 http://onsemi.com 7 package dimensions tssop20 dt suffix 20 pin plastic tssop package case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t
mc74act564 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74act564/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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